The invention relates to a full adder circuit and, in particular, a full adder circuit of a multiple logical level type using differential transistor pairs.
FIG. 1 shows a full adder circuit substantially similar to that shown in U.S. Pat. No. 3,519,810. This full adder circuit is of a three-input and two-output type using differential paired transistors in a tree-like configuration which is adapted for multiple logical levels. In FIG. 1 V.sub.DD and V.sub.SS represent a high and a low potential power source, respectively, and A, A, B, B, C, C show input signals and S, S show sum output signals. C', C' represent carry output signals and Vb represents a bias power source for a current source. The full adder circuit of FIG. 1 is characterized in that a sum output signal and carry output signal are almost simultaneously output due to the adoption of the multiple logical level circuit arrangement and that an arithmetic operation is carried out at high speed within a one-gate delay time range.
However, this circuit arrangement uses 26 transistors and thus a very great number of elements are required so as to provide a parallel multiplier using such transistors.